The present invention relates in general to devices and methods for reducing lead inductance in integrated circuit (IC) packages and, more specifically, to an integrated circuit package configuration for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages.
Integrated circuit (IC) packages typically contain small, generally rectangular integrated circuits referred to as IC xe2x80x9cdicexe2x80x9d or xe2x80x9cchipsxe2x80x9d. These IC dice come in an almost infinite variety of forms, including, for example, Dynamic Random Access Memory (DRAM) dice, Static Random Access Memory (SRAM) dice, Synchronous DRAM (SDRAM) dice, Sequential Graphics Random Access Memory (SGRAM) dice, flash Electrically Erasable Programmable Read-Only Memory (EEPROM) dice, and processor dice.
Packaged IC dice communicate with circuitry external to their packages through lead frames embedded in the packages. These lead frames generally include an assembly of leads that extend into the packages to connect to bond pads on the IC dice through thin wire bonds or other coonecting means and extend from the packages to teminate in pins or other terminals that connect to the external circuitry. Exemplary conventional lead frames include paddle-type wire-bond lead frames, which include a central die support and leads which extend to the preimeter of IC dice and connect to the dice through thin wire bonds, Leads-Over-Chip (LOC) lead frames, having leads which extend over an IC die to attach to and support the die while being electrically connected to the die through wire bonds or other connecting means, and Leads-Under-Chip (LUC) lead frames, having leads connected to the die typically through wire bonds.
As with all conductors, the leads in lead frames have an inductance associated with them that increases as the frequency of signals passing through the leads increases. This lead inductance is the result of two interactions: the interaction among magnetic fields created by signal currents flowing to and from an IC die through the leads (known as xe2x80x9cmutualxe2x80x9d inductance); and the interaction between the magnetic fields created by the signal currents flowing to and from the IC die through the leads and magnetic fields created by oppositely directed currents flowing to and from ground (known as xe2x80x9cselfxe2x80x9d inductance).
While lead inductance in IC packages for memory devices has not traditionally been troublesome because traditionally slow signal frequencies have made the inductance relatively insignificant, the ever-increasing frequencies of state of the art electronic systems have made lead inductance in IC packages significant. For example, overall performance of IC dice attached to leads in IC packages is slower than desirable because the inductance associated with the leads slows changes in signal current through the leads, causing signals to take longer to propagate through the leads. Also, digital signals propagating along the leads are dispersing (i.e., xe2x80x9cspreading outxe2x80x9d) because the so-called xe2x80x9cFourierxe2x80x9d components of various frequencies that make up the digital signals propagate through the inductance associated with the leads at different speeds, causing the components, and hence the digital signals themselves, to disperse along the leads, while mild dispersion can make the digital signals unrecognizable upon receipt. Impedance mismatches between the leads and IC dice or the leads and external circuitry, caused, in part, by the inductance associated with the leads, can distort normal signals propagating along the leads at the same time as the reflection signals. Further, magnetic fields created by signal currents propagating through the inductance associated with the leads can induce currents in nearby leads, causing so-called xe2x80x9ccrosstalkxe2x80x9d noise on the nearby leads. While these various effects can be troublesome in any electronic system, the modern trend toward 3.3 colt systems and away from 5.0 colt systems only serves to make these effects more noticeable and sugnificant. Also, the trend to ever increasing operating speeds for semiconductor devices further serves to make these effects more noticeable and significant. Particularly, such is present when the use of high density semiconductor devices operating at high frequencies requiring the use of packages having an increased number of connections to the semiconductor device is necessary.
Prior IC packages have been configured in an attempt to reduce carious effects of lead inductance as described above. For example, U.S. Pat. No. 5,214,845, assigned to the assignee of the present invention, employs a flexible, laminated sandwich assembly of an outer ground plane and an outer power plane dielectrically isolated from a series of conductive traces running therebetween. The traces and planes are connected to corresponding bond pads on an IC die at one end, and to leads on the other, as by thermocompression bonding (in case of a TAB embodiment), or by wire bonds. Such an arrangement obviously doubles the number required I/O connections by requiring ywo connections for each lead, and thus necessitates additional assembly time and increases the possibility of a faulty connection. Further, the flexible sandwich assembly constitutes an additional element of the package, increasing material cost.
Another approach to reducing the inductance effects described above is diclosed in U.S. Pat. No. 5,559,306, in which metal plates are employed above and below leads extending to the exterior of plastic and ceramic packages to effect reduction of self and mutual inductance. However, such configurations as diclosed appear to require relatively complex fabrication techniques to locate and fix the plates relative to the die and lead fingers or other conductors for subsequent transfer molding of a filled-polymer package thereabout, while the ceramic package embodiment is not cost-effective for high-volume, commercial packaging.
Accordingly, the inventors have recognized the need for a low-cost, reduced-inductance IC package configuration and readily-available materials, equipment, and fabrication techniques for semiconductor devices.
The present invention relates in general to devices and methods for reducing lead inductance in integrated circuit (IC) packages and, more specifically, to an integrated circuit package configuration for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages. The integrated circuit package of the present invention comprises a substrate, semiconductor device, insulating covering or coating, if desired, a semiconductor device retainer, lead frame, and wire bond interconnections.